This invention relates to apparatus for scanning an addressable memory and, more particularly, to such apparatus wherein the memory may be scanned in a step-wise manner in accordance with periodic clock pulses or in response to a selective scan advance circuit to, for example, scan the memory at a rate faster than the clock pulses.
In a typical electronic tuner, such as a tuner that can be used in a video or radio receiver, the particular channel, or broadcast frequency, to which the tuner can be tuned is controlled by a digital signal. Such a so-called digital electronic tuner is provided with an addressable memory into which digital signals representing corresponding channels, or broadcast frequencies, are written. Depending upon the address of the memory which is selected, the digital signal stored therein is read out and used to determine the tuning condition of the digital electronic tuner.
One example of a digital electronic tuner is disclosed in copending application Ser. No. 938,384, assigned to the assignee of the present invention. In this pending application, the tuning circuitry is a phase-locked loop having a voltage-controlled oscillator (VCO) whose oscillating frequency is determined by the digital signal read from the addressable memory, which oscillating signal is used as the local oscillating signal in the tuning circuit. Essentially, a programmable frequency divider divides the frequency of the oscillating signal generated by the VCO, which frequency-divided oscillating signal is phase-compared to a reference frequency. The dividing ratio of the programmable divider is established by the digital signal read from the addressed memory. As the dividing ratio changes, the frequency of the local oscillating signal generated by the VCO likewise changes.
Another example of an electronic digital tuner is disclosed in copending application Ser. No. 897,394, now U.S. Pat. No. 4,194,159, also assigned to the assignee of the present invention. In this example, a variable capacitance element, such as a Varicap diode, is controlled by an analog voltage which is derived from a digital signal read from the addressed memory. Another example of this type of electronic digital tuner is described in U.S. Pat. No. 3,940,702.
In a typical electronic digital tuner of the foregoing types, the addressable memory may be provided with only a limited number of storage locations such that only a limited number of predetermined channels, or broadcast frequencies, can be stored therein and rapidly selected. For example, such an addressable memory can be provided with six to eight addressable locations. In the event that the use wishes to sample the program information which then is being broadcast over these predetermined channels, or broadcast frequencies, a memory scanning circuit is activated so as to scan the addressable memory and thereby read, sequentially, each digital signal stored therein in a step-wise manner.
One type of scanning circuit which can be used to scan the addressable memory includes a clock pulse generator, an address counter and an address register. To initiate a scanning cycle, the clock pulse generator is activated so as to supply periodic clock pulses to the address counter. The count of the address counter is incremented (or decremented) in response to each clock pulse; and the instantaneous count of the address counter is stored in the address register and used as the memory address. The count of the address counter, and thus, the memory address, changes at a rate which is determined by the frequency of the clock pulses supplied to the counter. In general, such clock pulses are supplied at a relatively low rate, such as on the order of one clock pulse every four or five seconds, so as to change the memory address at a correspondingly slow rate. This enables the user to evaluate the program information which then is received over the channel, or broadcast frequency, that has been read from the memory. Once a desired channel, or broadcast frequency, is received, the scanning operation may be terminated.
It is appreciated that, in accordance with the foregoing example wherein representations of six to eight channels, or broadcast frequencies, are stored in the memory, and wherein the memory address is incremented (or decremented) once every four or five seconds, up to forty seconds may elapse until all of the predetermined channels, or broadcast frequencies, which are "stored" in the memory have been sampled. There are many applications wherein such a long delay in this scanning operation is undesired.